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PCA9541 2-to-1 I2C master selector with interrupt logic and reset
Product data sheet Supersedes data of 2003 Dec 02 2004 Oct 01
Philips Semiconductors
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
DESCRIPTION
The PCA9541 is a 2-to-1 I2C master selector designed for high reliability dual master I2C applications where system operation is required, even when one master fails or the controller card is removed for maintenance. The two masters (e.g., primary and back-up) are located on separate I2C-buses that connect to the same downstream I2C-bus slave devices. I2C commands are sent by either I2C-bus master and are used to select one master at a time. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master and the slave devices on the downstream I2C-bus. Three versions are offered for different architectures. PCA9541/01 with channel 0 selected at start-up, PCA9541/02 with channel 0 selected after start-up and after stop condition is detected, and PCA9541/03 with no channel selected after start-up. The interrupt outputs are used to provide an indication of which master has control of the bus. One interrupt input (INT_IN) collects downstream information and propagates it to the 2 upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the previous bus master know that it is not in control of the bus anymore and to indicate the completion of the bus recovery/initialization sequence. Those interrupts can be disabled and will not generate an interrupt if the masking option is set. A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a stop condition in order to set the downstream I2C-bus devices to an initialized state before actually switching the channel to the selected master. An interrupt is sent to the upstream channel when the recovery/initialization procedure is completed. An internal bus sensor senses the downstream I2C traffic and generates an interrupt if a channel switch occurs during a non-idle bus condition. This function is enabled when the PCA9541 recovery/initialization is not used. The interrupt signal informs the master that an external I2C-bus recovery/initialization needs to be performed. It can be disabled and an interrupt will not be generated. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage, which will be passed by the PCA9541. This allows the use of different bus voltages on each pair, so that 1.8 V 2.5 V or 3.3 V devices can communicate with 5 V devices without any additional protection. The PCA9541 does not isolate the capacitive loading on either side of the device so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels. External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 6.0 V tolerant. An active-LOW Reset Input allows the PCA9541 to be initialized. Pulling the RESET pin LOW resets the I2C state machine and configures the device to its default state as does the internal power on reset function.
FEATURES
* 2-to-1 bi-directional master selector * I2C interface logic; compatible with SMBus standards * PCA9541/01 powers-up with Channel 0 selected * PCA9541/02 powers-up with Channel 0 selected after STOP * PCA9541/03 powers-up with no channel selected and either * Active LOW Interrupt Input * 2 Active LOW Interrupt Outputs * Active LOW Reset Input * 4 address pins allowing up to 16 devices on the I2C-bus * Channel selection via I2C-bus * Bus initialization/recovery function * Bus traffic sensor * Low RdsON switches * Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and * No glitch on power-up * Supports hot insertion * Software identical for both masters * Low stand-by current * Operating power supply voltage range of 2.3 V to 5.5 V * 6.0 V tolerant Inputs * 0 to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114, * Latch-up testing is done to JESDEC Standard JESD78 which * Packages offered: SO16, TSSOP16, HVQFN16
APPLICATIONS
exceeds 100 mA 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 5 V buses master can take control of the bus condition detected (bus idle) on Channel 0
* High reliability systems with dual masters * Gatekeeper multiplexer on long single bus * Bus initialization/recovery for slave devices without hardware * Allows masters without arbitration logic to share resources
reset
2004 Oct 01
2
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO 16-Pin Plastic TSSOP 16-Pin Plastic HVQFN 16-Pin Plastic SO 16-Pin Plastic TSSOP 16-Pin Plastic HVQFN 16-Pin Plastic SO 16-Pin Plastic TSSOP 16-Pin Plastic HVQFN TEMPERATURE RANGE -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C ORDER CODE PCA9541D/01 PCA9541PW/01 PCA9541BS/01 PCA9541D/02 PCA9541PW/02 PCA9541BS/02 PCA9541D/03 PCA9541PW/03 PCA9541BS/03 TOPSIDE MARK PCA9541D/01 9541/01 41/1 PCA9541D/02 9541/02 41/2 PCA9541D/03 9541/03 41/3 DRAWING NUMBER SOT109-1 SOT403-1 SOT629-1 SOT109-1 SOT403-1 SOT629-1 SOT109-1 SOT403-1 SOT629-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
PIN CONFIGURATION
1 2 3 4 5 6 7 8 16 VDD 15 INT_IN 14 SDA_SLAVE 13 SCL_SLAVE 12 A3 11 A2 10 A1 9 A0 RESET 2 SCL_MST1 3 SDA_MST1 4 6 7 5 8 11 SCL_SLAVE SCL_MST0 1 16 SDA_MST0
SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 VSS
13 INT_IN 12 SDA_SLAVE 10 A3 9 A2 A1
INT0
15 INT0 VSS
TOP VIEW
SW02008
Figure 1. SO16/TSSOP16 pin configuration.
SW02034
Figure 2. HVQFN16 pin configuration.
PIN DESCRIPTION
SO/TSSOP PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HVQFN PIN NUMBER 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL INT0 SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 VSS A0 A1 A2 A3 SCL_SLAVE SDA_SLAVE INT_IN VDD FUNCTION Active LOW interrupt output 0 (external pull-up required) Serial data master 0 (external pull-up required) Serial clock master 0 (external pull-up required) Active LOW reset input (external pull-up required) Serial clock master 1 (external pull-up required) Serial data master 1 (external pull-up required) Active LOW interrupt output 1 (external pull-up required) Supply ground Address input 0 (externally held to GND or VCC) Address input 1 (externally held to GND or VCC) Address input 2 (externally held to GND or VCC) Address input 3 (externally held to GND or VCC) Serial clock slave (external pull-up required) Serial data slave (external pull-up required) Active LOW interrupt input (external pull-up required) Supply voltage
2004 Oct 01
3
INT1
A0
14 VDD
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
BLOCK DIAGRAM
PCA9541
SCL_MST0 INPUT FILTER STOP DETECTION BUS SENSOR
SDA_MST0
SCL_SLAVE A3 A2 A1 A0 RESET VDD POWER-ON RESET I2C-BUS CONTROL AND REGISTER BANK SLAVE CHANNEL SWITCH CONTROL LOGIC
SDA_SLAVE
SCL_MST1 INPUT FILTER STOP DETECTION
BUS RECOVERY/ INITIALIZATION
SDA_MST1
OSCILLATOR
INT0
INT_IN
INT1
INTERRUPT LOGIC
VSS
SW02009
Figure 3. Block diagram
2004 Oct 01
4
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
DEVICE ADDRESS
Following a START condition, the upstream master that wants to control the I2C-bus or make a status check must send the address of the slave it is accessing. The slave address of the PCA9541 is shown in Figure 4. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable pins and they must be pulled HIGH or LOW.
The 2 LSBS are used as a pointer to determine which register will be accessed. If the auto-increment flag is set (AI=1), the two least significant bits of the Command Code are automatically incremented after a byte has been read or written. This allows the user to program the registers sequentially or to read them sequentially. - During a Read operation, the contents of these bits will rollover to "00" after the last allowed register is accessed ("10"). - During a Write operation, the PCA9541 will acknowledge bytes sent to the IE and CONTROL registers but will not acknowledge a byte sent to the Interrupt Status Register since it is a read-only register. The 2 LSB's of the Command Code do not roll over to 00 but stays at 10.
1
1
1
A3 A2
A1 A0 R/W
FIXED
HARDWARE SELECTABLE
SW02011
Only the 2 least significant bits are affected by the AI flag. Unused bits must be programmed with zeroes. Any command code (Write operation) different from "000AI0000", "000AI0001", and "000AI0010" will not be acknowledged. At power-up, this register defaults to all zeros.
Figure 4. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected while logic 0 selects a write operation.
COMMAND CODE
Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9541, which will be stored in the Command Code register.
Table 1. Command Code Register
B1 0 B0 0 1 0 1 REGISTER NAME IE CONTROL ISTAT TYPE Read/Write Read/Write Read NOT ALLOWED REGISTER FUNCTION Interrupt Enable Control Switch Interrupt Status
0
0
0
AI
0
0
B1 B0
0 1
AUTO INCREMENT
REGISTER NUMBER
1
SW02302
Figure 5. Command Code
Each system master controls its own set of registers, however they can also read specific bits from the other system master.
PCA9541 INTERNAL REGISTER MAP
IE CONTROL ISTAT REG#00 REG#01 REG#10 IE CONTROL ISTAT
IE 0 CONTROL 0 ISTAT 0
IE 1 CONTROL 1 ISTAT 1
REG#00 REG#01 REG#10
MASTER 0 SCL_MST0 SDA_MST0
CONTROL 0
PCA9541
MASTER 1 SCL_MST1 SDA_MST1
CONTROL 1 7 6 5 4 3 2 1 0 SW02072
CONTROL REGISTER DETAIL
Figure 6. Internal register map
2004 Oct 01
5
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
INTERRUPT ENABLE AND CONTROL REGISTERS DESCRIPTION
When a master seeks control of the bus by connecting its I2C channel to the PCA9541 downstream channel, it has to write to the Control Register (Reg#01) Bits MYBUS and BUSON allow the master to take control of the bus. The MYBUS and the NMYBUS bits determine which master has control of the bus. Tables 4 and 5 explain which master gets control of the bus and how. There is no arbitration. Any master can take control of the bus when it wants regardless of whether the other master is using it or not. The BUSON and the NBUSON bits determine whether the upstream bus is connected or disconnected to/from the downstream bus. Internally, the state machine does the following: - If the combination of the BUSON and the NBUSON bits causes the upstream to be disconnected from the downstream bus, then that is done. So in this case, the values of the MYBUS and the NMYBUS do not matter. - If a master was connected to the downstream bus prior to the disconnect, then an interrupt is sent on the respective interrupt output in an attempt to let that master know that it is no longer connected to the downstream bus. This is indicated by setting the BUSLOST bit in the Interrupt Status Register. - If the combination of the BUSON and the NBUSON bits causes a master to be connected to the downstream bus and if there is no change in the BUSON bits since when the disconnect took effect, then the master requesting the bus is connected to the downstream bus. If it requests a bus initialization sequence, then it is performed. - If there is no change in the combination of the BUSON and the NBUSON bits and a new master wants the bus, then the downstream bus is disconnected from the old master that was using it and the new master gets control of it. Again, the bus initialization if requested is done. The appropriate interrupt signals are generated. After a master has sent the bus control request: 1. The previous master is disconnected from the I2C-bus. An interrupt to the previous master is sent through its INT line to let it know that it lost control of the bus. BUSLOST bit in the Interrupt Status Register is set. This interrupt can be masked by setting the BUSLOSTMSK bit to 1. 2. A built-in bus initialization/recovery function can take temporary control of the downstream channel to initialize the bus before making the actual switch to the new bus master. This function is activated by setting the BUSINIT to 1 by the master during the same write sequence as the one programming MYBUS and BUSON bits.
When activated and whether the bus was previously idle or not: - 9 clock pulses are sent on the SCL_SLAVE. - SDA_SLAVE line is released (HIGH) when the clock pulses are sent to SCL_SLAVE. This is equivalent to sending 8 data bits and a not acknowledge - Finally a STOP condition is sent to the downstream slave channel. This sequence will complete any read transaction which was previously in process and the downstream slave configured as a slave-transmitter should release the SDA line because the PCA9541 did not acknowledge the last byte. 3. When the initialization has been requested and completed, the PCA9541 sends an interrupt to the new master through its INT line and connects the new master to the downstream channel. BUSINIT bit in the Interrupt Status Register is set. The switch operation occurs after the master asking the bus control has sent a STOP command. This interrupt can be masked by setting the BUSINITMSK bit to 1. 4. When the bus initialization/recovery function has not been requested (BUSINIT=0), the PCA9541 connects the new master to the slave downstream channel. The switch operation occurs after the master asking the bus control has sent a STOP command. PCA9541 sends an interrupt to the new master through its INT line if the built-in bus sensor function detects a non-idle condition in the downstream slave channel at the switching time. BUSOK bit in the Interrupt Status Register is set. This means that a STOP condition has not been detected in the previous bus communication and that an external bus recovery/initialization must be performed. If an idle condition has been detected at the switching time, no interrupt will be sent. This interrupt can be masked by setting the BUSOKMSK bit to 1. Interrupt status can be read. See paragraph INTERRUPT STATUS REGISTER DESCRIPTION for more information. The MYTEST and the NMYTEST bits cause the interrupt pins of the respective masters to be activated for a "functional interrupt test". NOTES: 1. The regular way to proceed is that a master asks to take the control of the bus by programming MYBUS and BUSON bits. Nevertheless, the same master can also decide to give up the control of the bus and give it to the other master. This is also done by programming the MYBUS and BUSON bits. 2. Any writes either to the Interrupt Enable Register or the Control Register cause the respective register to be updated on the 9th clock cycle, i.e. on the rising edge of the acknowledge clock cycle. 3. The actual switch from one channel to another or the switching off of both the channels happens on a STOP command.
2004 Oct 01
6
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
Register 0: Interrupt Enable (IE) Register (B1B0 = 00)
This register allows a master to read and/or write (if needed) Mask options for its own channel. The Interrupt Enable Register described below is identical for both the masters. Nevertheless, there are physically 2 internal Interrupt Enable Registers, one for each upstream channel. When Master 0 reads/writes in this register, the internal Interrupt Enable Register 0 will be accessed. When Master 1 reads/writes in this register, the internal Interrupt Enable Register 1 will be accessed. BIT SYMBOL 7 0 6 0 5 0 4 0 3 BUSLOSTMSK 2 BUSOKMSK 1 BUSINITMSK 0 INTINMSK
Table 2. Register 0
BIT 0 SYMBOL INTINMSK READ/ WRITE R/W DEFAULT 0 DESCRIPTION 0: Interrupt on INT_IN will generate an interrupt on INT 1: Interrupt on INT_IN will not generate an interrupt on INT (masked) 0: After connection is requested and Bus Initialization requested (BUSINIT = 1), an interrupt on INT will be generated when the bus initialization is done. Note: Channel switching is done after bus initialization completed. 1: After connection is requested and Bus Initialization requested (BUSINIT = 1), an interrupt on INT will not be generated when the bus initialization is done (masked). Note: Channel switching is done after bus initialization completed. 0: After connection is requested and Bus Initialization not requested (BUSINIT = 0), an interrupt on INT will be generated when a non-Idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment. Note: Channel switching is done automatically after the STOP command. 1: After connection is requested and Bus Initialization not requested (BUSINIT = 0), an interrupt on INT will not be generated when a non-Idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment (masked). Note: Channel switching is done automatically after the STOP command. 0: An interrupt on INT will be generated after the other master has been been disconnected 1: An interrupt on INT will not be generated after the other master has been been disconnected.
1
BUSINITMSK
R/W
0
2
BUSOKMSK
R/W
0
3
BUSLOSTMSK
R/W
0
4 5 6 7
NOT USED NOT USED NOT USED NOT USED
R only R only R only R only
0 0 0 0
NOTE: Default values are the same for PCA9541/01, PCA9541/02, and PCA9541/03
2004 Oct 01
7
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
Register 1: Control Register (B1B0 = 01)
x stands for 0 or 1 and is applied to the master that reads or writes in the Control Register explained below The Control Register described below is identical for both the masters. Nevertheless, there are physically 2 internal Control Registers, one for each upstream channel. When master 0 reads/writes in this register, the internal Control Register 0 will be accessed. When master 1 reads/writes in this register, the internal Control Register 1 will be accessed. BIT SYMBOL 7 NTESTON 6 TESTON 5 0 4 BUSINIT 3 NBUSON 2 BUSON 1 NMYBUS 0 MYBUS
Table 3. Register 1
BIT SYMBOL READ/ WRITE R/W DEFAULT See Table 6 See Table 6 See Table 6 See Table 6 0 0 0 0: a Logic Level High to the INT line is sent (interrupt cleared) 1: a Logic Level Low to the INT line is sent (interrupt generated) 0: a Logic Level High to the INT line of the other channel is sent (interrupt cleared) 1: a Logic Level Low to the INT line of the other channel is sent (interrupt generated) DESCRIPTION MYBUS bit along with the NMYBUS bit decides which upstream channel is connected to the downstream channel See Table 4 NMYBUS bit is a copy of the MYBUS bit for the other channel See Table 4 BUSON bit along with the NBUSON bit decides whether any upstream channel is connected to the downstream channel or not See Table 5 NBUSON bit is a copy of the BUSON bit for the other channel See Table 5 0: Bus initialization not requested 1 : Bus initialization requested
0
MYBUS
1
NMYBUS
R only
2
BUSON
R/W
3
NBUSON
R only
4 5 6
BUSINIT NOT USED TESTON
R/W R only R/W
7
NTESTON
R only
0
2004 Oct 01
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Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
Table 4. MYBUS and NMYBUS Truth Table
NMYBUS 0 1 0 1 MYBUS 0 0 1 1 SLAVE CHANNEL to the switching initiator to the other channel to the other channel to the switching initiator
Table 5. BUSON and NBUSON Truth Table
NBUSON 0 1 0 1 BUSON 0 0 1 1 SLAVE CHANNEL OFF ON ON OFF
NOTES: 1. Switch to the new channel is done when the master initiating the switch request sends a STOP command to the PCA9541. 2. If Master 0 wants to change the connection to the downstream channel in any way, it needs to write to its Control Register (Reg#01), and then send a STOP command because an update of the connection to the downstream according to the values in the two internal Control Registers happens only on a STOP command. Writing to one control register followed by a STOP condition on the other Master's channel will not cause an update to the downstream connection. 3. When both masters request a switch to their own channel at the same time, the master who last wrote to its control register before the PCA9541 receives a STOP command wins the switching sequence. There is no arbitration performed. 4. Auto Increment feature (AI=1) allows to program the PCA9541 in 4 bytes: - - - - - - Start 111A3A2A1A0 + 0 00010000 Data Reg#00 Data Reg#01 Stop PCA9541 Address + Write Select Reg#00 with AI = 1 Interrupt Enable Register Data Control Register Data
Table 6. Default Control Register Values
BIT VERSION PCA9541/01 SYMBOL MST_0 MST_1 MST_0 PCA9541/02 MST_1 MST_0 PCA9541/03 PCA9541/02 (AFTER STOP) MST_1 MST_0 MST_1 7 NTESTON 0 0 0 0 0 0 0 0 6 TESTON 0 0 0 0 0 0 0 0 5 NOT USED 0 0 0 0 0 0 0 0 4 BUSINIT 0 0 0 0 0 0 0 0 3 NBUSON 0 1 0 0 0 0 0 1 2 BUSON 1 0 0 0 0 0 1 0 1 NMYBUS 0 1 0 1 0 1 0 1 0 MYBUS 0 0 0 0 0 0 0 0
2004 Oct 01
9
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
Table 7 describes which command needs to be written to the Control Register when a master device wants to take control of the I2C-bus. Byte written to the Control Register is a function of the current I2C-bus control status performed after an initial reading of the Control Register. Current status of the I2C-bus is determined by the bits MYBUS, NMYBUS, BUSON and NBUSON is one of the following: - The master reading its Control Register does not have control and the I2C-bus is off. - The master reading its Control Register does not have control and the I2C-bus is on. - The master reading its Control Register has control and the I2C-bus is off. - The master reading its Control Register has control and the I2C-bus is on.
`I2C-bus off' means that upstream and downstream channels are not connected together. `I2C-bus on' means that upstream and downstream channels are connected together. Remark: Only the 4 LSBs of the Control Register are described in Table 7 since only those bits control the I2C-bus control. The logic value for the 4 MSBs is specific to the application and are not discussed in the table. The Read sequence is performed by the master as following: S -- 111xxxx0 -- 000x0001 -- Sr -- 111xxxx1 -- DataRead -- P The Write sequence is performed by the master as following: S -- 111xxxx0 -- 000x0001 -- DataWritten -- P
Table 7. Bus control sequence
Read Control Register performed by the Master Byte Read only the 4 LSBs are shown Hex 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Bus off Bus off Bus off Bus off Bus on Bus on Bus on Bus on Bus on Bus on Bus on Bus on Bus off Bus off Bus off Bus off Has control No control No control Has control Has control No control No control Has control Has control No control No control Has control Has control No control No control Has control 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Write Control Register performed by the Master Byte Written only the 4 LSBs are shown (see Note 1) Binary x1x0 x1x0 x1x1 x1x1 No write required x1x0 x1x1 No write required No write required x0x0 x0x1 No write required x0x0 x0x0 x0x1 x0x1 Hex 0x4 0x4 0x5 0x5 - 0x4 0x5 - - 0x0 0x1 - 0x0 0x0 0x1 0x1 Bus on Bus on, Take control Bus on, Take control Bus on No change Take control Take control No change No change Take control Take control No change Bus on Bus on, Take control Bus on, Take control Bus on
Status
NBUSON
BUSON
NMYBUS
MYBUS
Action performed to take Mastership
NOTES: 1. x0x0 = 0x0, 0x2, 0x8, 0xA x0x1 = 0x1, 0x3, 0x9, 0xB x1x0 = 0x4, 0x6, 0xC, 0xE x1x1 = 0x5, 0x7, 0xD, 0xF
2004 Oct 01
10
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
INTERRUPT STATUS REGISTERS DESCRIPTION
The PCA9541 provides 4 different types of interrupt: 1. To indicate to the former I2C-bus master that it is not in control of the bus anymore. 2. To indicate to the new I2C-bus master that: - The bus recovery/initialization has been performed and that the downstream channel connection has been done (built-in bus recovery/initialization active). - A "bus not well initialized" condition has been detected by the PCA9541 when the switch has been done (built-in bus recovery/initialization not active). This information can be used by the new master to initiate its own bus recovery/initialization sequence. 3. Indicate to both I2C upstream masters that a downstream interrupt has been generated through the INT_IN pin. 4. Functionality wiring test. downstream I2C traffic) detects a non-idle condition (previous bus channel connected to the downstream slave channel, was between a START and STOP condition), then an interrupt to the new master is sent (INT line goes LOW). This interrupt tells the new master that an external bus recovery/initialization must be performed. By setting the BUSOKMSK bit to 1, the interrupt is masked and the new master does not receive an interrupt (INT line does not go LOW). NOTE: In this particular situation, after the switch to the new master is performed, a read of the Interrupt Status Register is not possible if the switch happened in the middle of a read sequence because the new master does not have control of the SDA line
Downstream interrupt
An interrupt can also be generated by a downstream device by asserting the INT_IN pin LOW. When INT_IN is asserted LOW and if both INTINMSK bits are not set to 1 by either master, INT0 and INT1 both go LOW. By setting the INTINMSK bit to 1 by a master and/or the INTINMSK bit to 1 by the other master, the interrupt(s) is (are) masked and the corresponding masked channel(s) does (do) not receive an interrupt (INT0 and/or INT1 line does (do) not go LOW).
Bus control lost interrupt
When an upstream master takes control of the I2C-bus while the other channel was using the downstream channel, an interrupt is generated to the master losing control of the bus (INT line goes LOW to let the master know that it lost the control of the bus) immediately after disconnection from the downstream channel. By setting the BUSLOSTMSK bit to 1, the interrupt is masked and the upstream master that lost the I2C-bus control does not receive an interrupt (INT line does not go LOW).
Functional test interrupt
A master can send an interrupt to itself to test its own INT wire or send an interrupt to the other master to test its INT line. This is done by: - Setting the TESTON bit to 1 to test its own INT line. - Setting the NTESTON bit to 1 to test the other master INT line. Setting the TESTON and/or NTESTON bits to 0 by a master will clear the interrupt(s). NOTE: Interrupt outputs have an open-drain structure. Interrupt input does not have any internal pull-up resistor and must not be left floating (e.g., pulled high to VCC through resistor) in order to avoid any undesired interrupt conditions.
Recovery/initialization interrupt
Before switching to a new upstream channel, an automatic bus recovery/initialization can be performed by the PCA9541. This function is requested by setting the BUSINIT bit to 1. When the downstream bus has been initialized, an interrupt to the new master is generated (INT line goes LOW). By setting the BUSINITMSK bit to 1, the interrupt is masked and the new master does not receive an interrupt (INT line does not go LOW). When the automatic bus recovery/initialization is not requested, if the built-in bus sensor function (sensing permanently the
2004 Oct 01
11
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
Register 2: Interrupt Status Register (B1B0 = 10)
The Interrupt Status Register for both the masters is identical and is described below. Nevertheless, there are physically 2 internal Interrupt Registers, one for each upstream channel. When Master 0 reads this register, the internal Interrupt Register 0 will be accessed. When Master 1 reads this register, the internal Interrupt Register 1 will be accessed. BIT SYMBOL 7 NMYTEST 6 MYTEST 5 0 4 0 3 BUSLOST 2 BUSOK 1 BUSINIT 0 INTIN
Table 8. Register 2
BIT 0 SYMBOL INTIN READ/ WRITE R only DEFAULT 0 DESCRIPTION 0: No interrupt on interrupt input (INT_IN) 1: Interrupt on interrupt input (INT_IN) 0: No interrupt generated by the bus recovery/initialization function 1 BUSINIT R only 0 1: Interrupt generated by the bus recovery/initialization function - recovery/initialization done 0: No interrupt generated by bus sensor function 2 BUSOK R only 0 1: Interrupt generated by bus sensor function (masked when bus recovery/initialization requested) - Bus was not idle when the switch occurred 0: No interrupt generated to the previous master when switching to the new one is initiated 3 BUSLOST R only 0 1: Interrupt generated to the previous master when switching to the new one is initiated
4 5 6
NOT USED NOT USED MYTEST
R only R only R only
0 0 0 0: No interrupt generated by TESTON bit f (TESTON = 0) 1: Interrupt generated by TESTON bit (TESTON = 1) 0: No interrupt generated due to NTESTON bit from the other master (NTESTON = 0 from the other master)
7
NMYTEST
R only
0
1: Interrupt generated due to TESTON bit from the other master (NTESTON = 1 from the other master)
NOTES: 1. Interrupt on a master is cleared after TESTON bit is cleared the same master or NTESTON bit is cleared by the other master. 2. If the interrupt condition remains on INT_IN after the Read sequence, another interrupt will be generated (if the interrupt has not been masked) 3. Default values are the same for PCA9541/01, PCA9541/02 and PCA9541/03 4. Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if: - INT_IN lines goes HIGH for INTIN bit - TESTON bit is cleared for MYTEST bit - NTESTON bit is cleared for NMYTEST bit 5. BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register gets cleared after a Read of the same register is done. Precisely, the register gets cleared on the second clock pulse during the read operation.
2004 Oct 01
12
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
POWER-ON RESET
When power is applied to VDD, an internal Power-On Reset holds the PCA9541 in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the internal registers are initialized to their default states, with: Default PCA9541/01 PCA9541/02 PCA9541/03 Channel 0 Channel 0 No Channel n Stop Detect
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9541 are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another.
Vpass vs. VDD 5.0 4.5 MAXIMUM 4.0 TYPICAL 3.5 Vpass 3.0 2.5 2.0 1.5 1.0 2.0 2.5 3.0 3.5 4.0 VDD 4.5 5.0 5.5 MINIMUM
1. PCA9541/01: after power-up and/or insertion of the device in the main I2C-bus, the upstream Channel 0 and the downstream slave channel are connected together. 2. PCA9541/02: after power-up and/or insertion of the device in the main I2C-bus, the upstream Channel 0 and the downstream slave channel are connected together after a STOP condition has been detected by the PCA9541/02 on Channel 0. - If the bus was not idle, Channel 0 and the downstream slave device will be connected together as soon as a STOP condition occurs at the conclusion of the transmission sequence on Channel 0. - If the bus was idle, then Channel 0 is connected to the downstream slave channel after a STOP condition is detected on Channel 0. This I2C-bus command may or may not be addressed to the PCA9541/02. - If a switch to channel 1 (initiated by the master on channel 1) is requested (before or after the default switch to Channel 0 has been performed), the upstream channel 1 is connected to the downstream slave channel when the master located in Channel 1 sends the STOP command. 3. PCA9541/03: after power-up and/or insertion of the device in the main I2C-bus, no channel will be connected to the downstream channel. The device is ready to receive a START condition and its address by a master. If either register writes to its Control Register, then the connection between the upstream and the downstream channels is determined by the values on the Control Registers. Thereafter, VDD must be lowered below 0.2 V to reset the device.
SW00820
Figure 7. Vpass voltage Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in the DC Characteristics section of this datasheet). In order for the PCA9541 to act as a voltage translator, the Vpass voltage should be equal to, or lower than the lowest bus voltage. For example, if the main buses were running at 5 V, and the downstream bus was 3.3 V, then Vpass should be equal to or below 3.3 V to effectively clamp the downstream bus voltages. Looking at Figure 7, we see that Vpass (max.) will be at 3.3 V when the PCA9541 supply voltage is 3.5 V or lower so the PCA9541 supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 16). More Information on voltage translation can be found in Application Note AN262 PCA954X family of I 2C/SMBus multiplexers and switches.
EXTERNAL RESET
A reset can be accomplished by holding the RESET pin LOW for a minimum of tW. The PCA9541 registers and I2C state machine will be held in their default states until the RESET input is once again HIGH. This input typically requires a pull-up resistor to VDD. Default states are: - I2C upstream Channel 0 connected to the I2C downstream channel for the PCA9541/01 - no I2C upstream channel connected to the I2C downstream channel for the PCA9541/02 with Channel 0 connected to the downstream I2C channel after detection of a STOP on the upstream channel. - no I2C upstream channel connected to the I2C downstream channel for the PCA9541/03.
2004 Oct 01
13
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 9).
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see FIgure 8).
System configuration
A device generating a message is a transmitter: a device receiving is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 10).
SDA
SCL data line stable; data valid change of data allowed
SW00363
Figure 8. Bit transfer
SDA
SDA
SCL S START condition P STOP condition
SCL
SW00365
Figure 9. Definition of start and stop conditions
SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
I2C MULTIPLEXER
SLAVE
SW00366
Figure 10. System configuration
2004 Oct 01
14
Philips Semiconductors
Product data sheet
2-to-1 I2C master selector with interrupt logic and reset
PCA9541
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition 1 2 8 9 clock pulse for acknowledgement
SW00368
Figure 11. Acknowledgement on the
I2C-bus
2004 Oct 01
15
Philips Semiconductors
2004 Oct 01
S 1 1 start condition S 1 1 1 start condition
2-to-1 I2C master selector with interrupt logic and reset
SLAVE ADDRESS
COMMAND CODE REGISTER
DATA MASK REGISTER
DATA CONTROL REGISTER
1
A3
A2 A1
A0
0 R/W
A
0
0
0
1
0
0
0
0
A
A
A
P
acknowledge from slave
Auto increment
acknowledge from slave
acknowledge from slave
acknowledge from slave
Stop condition
SW02306
Figure 12. Write to the Mask and Control Registers using the Auto-Increment (AI) bit NOTE: If a 3rd data byte is sent, it will not be acknowledged by the PCA9541.
SLAVE ADDRESS
COMMAND CODE ACCESS TO REGISTER XX = 00, 01, OR 10
XX = 00 : INTERRUPT ENABLE REGISTER XX = 01 : CONTROL REGISTER XX = 10 : INT REGISTER SLAVE ADDRESS
CONTROL REGISTER INT REGISTER INTERRUPT ENABLE REGISTER
INT REGISTER INTERRUPT ENABLE REGISTER CONTROL REGISTER
A3 A2
A1
A0
0 R/W
A
0
0
0
1
0
0
X
X
A
Sr
1
1
1
A3 A2 A1 A0
1
A
A
A
A
P
acknowledge from slave
Auto Increment
acknowledge from slave
re-start condition
R/W acknowledge from slave
acknowledge from master
acknowledge from master
no acknowledge- stop from master condition
15 Figure 13. Read the 3 registers using the Auto-Increment (AI) bit NOTE: If a 4th data byte is read, the first Register will be accessed.
SW02307
PCA9541
Product data sheet
Philips Semiconductors
2004 Oct 01 16
2-to-1 I2C master selector with interrupt logic and reset
SDA_MST0
S 1 1
SLAVE ADDRESS
COMMAND CODE REGISTER
DATA CONTROL REGISTER
AFTER THE STOP CONDITION, MASTER 1 IS DISCONNECTED FROM THE DOWNSTREAM CHANNEL 0 A P stop condition
1
A3 A2
A1
A0
0 R/W
A
0
0
0
AI
0
0
0
1
A
0
0
0
1
0
0
0
start condition
acknowledge from slave
Auto Increment
acknowledge from slave
BUSINIT BUSON MYBUS acknowledge from slave
SCL_MST0
INT1
IF THE INTERRUPT IS NOT MASKED (BUSLOSTMSK = 0)
SCL_SLAVE SDA_SLAVE
1
2
3
4
5
6
7
8
9
P
INT0
IF THE INTERRUPT IS NOT MASKED (BUSINITMSK = 0) MASTER 0 HAS CONTROL OF THE BUS MASTER 1 HAS CONTROL OF THE BUS PCA9541 HAS CONTROL OF THE BUS
MASTER 0 MUST WAIT FOR THE "BUS FREE TIME" VALUE (BETWEEN STOP AND START) DEFINED IN THE I2C SPECIFICATION BEFORE SENDING COMMANDS TO THE DOWNSTREAM DEVICES
SW02308
Figure 14. Write to the control register and switch from channel 1 to channel 0 (bus recovery/initialization requested) NOTE: We assume that a Read of the control register was done by Master 1 and that 000x1010 was read.
PCA9541
Product data sheet
Philips Semiconductors
2004 Oct 01 17
SDA_MST0
S 1 1
SLAVE ADDRESS
COMMAND CODE REGISTER
DATA CONTROL REGISTER
AFTER THE STOP CONDITION, MASTER 1 IS DISCONNECTED FROM THE DOWNSTREAM CHANNEL AND MASTER 0 IS CONNECTED TO THE DOWNSTREAM CHANNEL
2-to-1 I2C master selector with interrupt logic and reset
1
A3 A2
A1
A0
0 R/W
A
0
0
0
AI
0
0
0
1
A
0
0
0
0
0
0
0
0
A
P stop condition
start condition
acknowledge from slave
Auto Increment
acknowledge from slave
acknowledge from slave
SCL_MST0
INT1
IF THE INTERRUPT IS NOT MASKED (BUSLOSTMSK = 0)
INT0
IF MASTER 1 WAS NOT IDLE AT THE SWITCHING MOMENT AND THE INTERRUPT IS NOT MASKED (BUSOKMSK = 0)
MASTER 1 HAS CONTROL OF THE BUS
MASTER 0 HAS CONTROL OF THE BUS
MASTER 0 MUST WAIT FOR THE "BUS FREE TIME" VALUE (BETWEEN STOP AND START) DEFINED IN THE I2C SPECIFICATION BEFORE SENDING COMMANDS TO THE DOWNSTREAM DEVICES
SW02309
Figure 15. Write to the control register and switch from channel 1 to channel 0 (bus recovery/initialization not requested)
PCA9541
Product data sheet
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
TYPICAL APPLICATION
3.3 V VDD MASTER 0 SCL0 SDA0 RESET0 SLAVE 2 INT0 VSS INT0 INT_IN INT SDA SCL SCL_MST0 VDD
SDA_MST0
RESET
SD1 SC1
3.3 V VDD MASTER 1 SCL1 SDA1 RESET1
PCA9541
SDA SCL SDA SCL
SLAVE 1 SCL_MST1 SDA_MST1
SLAVE 3
INT1 VSS
INT1 A3 A2 A1 A0 VSS
SLAVE CARD
SW02010
Figure 16. Typical application
SPECIFIC APPLICATIONS
The PCA9541 is a 2-to-1 I2C master selector designed for dual master, high reliability I2C applications, where continuous maintenance and control monitoring is required even if one master fails or its controller card is removed for maintenance. The PCA9541 can also be used in other applications, such as where masters share the same resource but cannot share the same bus, as a gatekeeper multiplexer in long single bus applications or as a bus initialization/recovery device.
HIGH RELIABILITY SYSTEMS
In a typical multi-point application, shown in Figure 17, the two masters (e.g., primary and back-up) are located on separate I2C-buses that connect to multiple downstream I2C-bus slave cards/devices via a PCA9541/01 for non-hot swap applications or the PCA9541/02 for hot swap applications to provide high reliability of the I2C-bus.
MASTER 0
PCA9541
PCA9541
PCA9541
PCA9541
PCA9541
PCA9541
PCA9541
SDA0
PCA9541
SCL1 SDA1
SR02462
Figure 17. High Reliability Backplane Application 2004 Oct 01 18
MASTER 1
SCL0
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
I2C commands are sent via the primary or back-up master and either master can take command of the I2C-bus. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master and the slave devices located on the cards. For even higher reliability in multi-point backplane applications, two dedicated masters can be used for every card as shown in Figure 18.
GATEKEEPER MULTIPLEXER
The PCA9541/03 can act as a gatekeeper multiplexer in applications where there are multiple I2C devices with the same fixed address (e.g., EEPROMs with address of "Z" as shown in Figure 20) connected in a multi-point arrangement to the same I2C-bus. Up to 16 hot swappable cards/devices can be multiplexed to the same bus master by using one PCA9541/03 per card/device. Since each PCA9541/03 has its own unique address (e.g., "A", "B", "C", etc), the EEPROMs can be connected to the master, one at a time, by connecting one PCA9541/03 (Master 0 position) while keeping the rest of the cards/devices isolated (off position). The alternative, shown with dashed lines, is to use a PCA9548 1-to-8 channel switch on the master card and run 8 I2C-buses, one to each EEPROM card, to multiplex the master to each card. The number of card pins used is the same in either case, but there are 7 less pairs of SDA/SCL traces on the PC board if the PCA9541/03 is used.
MASTER 0
SCL0 SDA0
PCA9541
SCL1 SDA1
MASTER 0
SCL0 SDA0
PCA9541
SCL1 SDA1
MASTER 1
MASTER 1
MASTER 0
PCA9541
PCA9541
PCA9541
PCA9541
PCA9541
PCA9541
PCA9541
PCA9541
MASTER 0
SCL0 SDA0
PCA9541
SCL1 SDA1
MASTER 1
A
EEPROM PCA9548
B
EEPROM
C
EEPROM
D
EEPROM
E
EEPROM
F
EEPROM
G
EEPROM
H
EEPROM
MASTER 0
SCL0 SDA0
PCA9541
SCL1 SDA1
MASTER 1
Z
SR02463
Z
Z
Z
Z
Z
Z
Z
SW02099
Figure 18. Very High Reliability Backplane Application
Figure 20. Gatekeeper Multiplexer Application
MASTERS WITH SHARED RESOURCES
Some masters may not be multi-master capable or some masters may not work well together and continually lock up the bus. The PCA9541 can be used to separate the masters, as shown in Figure 19, but still allow shared access to slave devices, such as Field Replaceable Unit (FRU) EEPROMs or temperature sensors.
ASSEMBLY A PCA9541 SLAVE A0 ASSEMBLY B PCA9541 SLAVE B0 SLAVE B1 SDA/SCL SLAVE B2 SLAVE A1 SDA/SCL MASTER A SLAVE A2
BUS INITIALIZATION/RECOVERY
If the I2C-bus is hung, I2C devices without a hardware reset pin (e.g., Slave 1 and 2 in Figure 21) can be isolated from the master by the PCA9541/03. The PCA9541/03 disconnects the bus when it is reset via the hardware reset line, restoring the master's control of the rest of the bus (e.g., Slave 0). The bus master can then command the PCA9541/03 to send 9 clock pulses/ stop condition to reset the downstream I2C devices before they are reconnected to the master or leave the downstream devices isolated.
SDA/SCL MASTER
MAIN MASTER
SLAVE 1 SDA SCL SLAVE 2
PCA9541/03
MASTER B
SLAVE I2C-bus
SLAVE 0
SW02101
RESET
Figure 19. Masters with Shared Resources Application
SW02100
Figure 21. Bus Initialization/Recovery Application
2004 Oct 01
19
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VDD VI II IO IDD ISS Ptot Tstg Tamb PARAMETER DC supply voltage DC input voltage DC input current DC output current Supply current Supply current total power dissipation Storage temperature range Operating ambient temperature CONDITIONS RATING -0.5 to +7.0 -0.5 to +7.0 20 25 100 100 400 -60 to +150 -40 to +85 UNIT V V mA mA mA mA mW C C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
DC CHARACTERISTICS
SYMBOL Supply VDD IDD Istb VPOR VIL VIH IOL IL Ci VIL VIH ILI Ci Pass Gate RON Supply voltage Supply current Standby current
VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. (See page 21 for VDD = 3.6 V to 5.5 V) PARAMETER TEST CONDITIONS LIMITS MIN 2.3 Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 0 kHz no load; VI = VDD or VSS -- -- -- -0.5 0.7VDD VOL = 0.4 V VOL = 0.6 V VI = VDD or VSS VI = VSS 3 6 -1 -- -0.5 0.7VDD VI = VDD or VSS VI = VSS VCC = 3.0 V to 3.6 V, VO = 0.4 V, IO = 15 mA VCC = 2.3 V to 2.7 V, VO = 0.4 V, IO = 10 mA Vswin = VDD = 3.3 V; Iswout = -100 A VP Pass Switch output voltage out ut Vswin = VDD = 3.0 V to 3.6 V; Iswout = -100 A Vswin = VDD = 2.5 V; Iswout = -100 A Vswin = VDD = 2.3 V to 2.7 V; Iswout = -100 A IL IOL Leakage current LOW-level output current VI = VDD or VSS VOL = 0.4 V INT0 and INT1 outputs 3 -- -- mA NOTE: 1. VDD must be lowered to 0.2 V in order to reset part. -1 -- 5 7 -- 1.6 -- 1.1 -1 TYP -- 152 10 1.5 -- -- -- -- -- 4 -- -- -- 2 14 17 2.2 -- 1.5 -- -- MAX 3.6 200 100 2.1 0.3VDD 6 -- -- +1 5 +0.3VDD 6 +1 3 30 55 -- 2.8 -- 2.0 +1 A V UNIT
V A A V V V mA A pF V V A pF
Power-on reset voltage (Note 1) LOW-level input voltage HIGH-level input voltage LOW-level out ut current output Leakage current Input capacitance LOW-level input voltage HIGH-level input voltage Input leakage current Input capacitance
Input SCL; input/output SDA (upstream and downstream channels)
Select inputs A0 to A3 / INT_IN / RESET
Switch resistance
2004 Oct 01
20
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
DC CHARACTERISTICS
SYMBOL Supply VDD IDD Supply voltage Supply current
VDD = 3.6 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. (See page 20 for VDD = 2.3 V to 3.6 V) PARAMETER TEST CONDITIONS LIMITS MIN 3.6 Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 0 kHz no load; VI = VDD or VSS -- TYP -- 349 MAX 5.5 600 UNIT
V A
Istb VPOR VIL VIH IO OL IIL IIH Ci VIL VIH ILI Ci Pass Gate RON VPass IL IOL
Standby current Power-on reset voltage (Note 1) LOW-level input voltage HIGH-level input voltage LOW-level LOW level output current LOW-level input current HIGH-level input current Input capacitance LOW-level input voltage HIGH-level input voltage Input leakage current Input capacitance Switch resistance Switch output voltage Leakage current LOW-level output current
-- -- -0.5 0.7VDD
10 1.5 -- -- -- -- -- -- 4 -- -- -- 2 12 3.6 -- -- --
200 2.1 0.3VDD 6 -- -- 10 100 6 +0.3VDD 6 +50 5 24 -- 4.5 +100 --
A V V V mA mA A A pF V V A pF V V A mA
Input SCL; input/output SDA (upstream and downstream channels)
VOL = 0.4 V VOL = 0.6 V VI = VSS VI = VDD VI = VSS
3 6 -10 -- -- -0.5 0.7VDD
Select inputs A0 to A3 / INT_IN / RESET
VI = VDD or VSS VI = VSS VCC = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA Vswin = VDD = 5.0 V; Iswout = -100 A Vswin = VDD = 4.5 to 5.5 V; Iswout = -100 A VI = VDD or VSS VOL = 0.4 V
-1 -- 4 -- 2.6 -1 3
INT0 and INT1 outputs NOTE: 1. VDD must be lowered to 0.2 V in order to reset part.
2004 Oct 01
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Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
AC CHARACTERISTICS
SYMBOL tpd fSCL fSCLIR tBUF tHD;STA tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tR tF Cb tSP tVD:DATL tVD:DATH tVD:ACK tiv tir Lpwr Hpwr RESET tW trst tREC:STA Pulse width LOW reset Reset time (SDA clear) Recovery to Start5, 6 4 500 0 -- -- -- 4 500 0 -- -- -- ns ns ns PARAMETER Propagation delay from SDA to SDn or SCL to SCn SCL clock frequency SCL bus initialization/recovery clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Set-up time for STOP condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Capacitive load for each bus line Pulse width of spikes which must be suppressed by the input filter Data valid (HL)4 Data valid (LH)4 Data valid Acknowledge INT_in to INT1 or INT2 active valid time INT_in to IINT1 or INT2 inactive delay time LOW level pulse width rejection or INT_in input HIGH level pulse width rejection or INT_in input STANDARD-MODE I2C-bus MIN -- 0 50 4.7 4.0 4.7 4.0 4.7 4.0 02 250 -- -- -- -- -- -- -- -- -- 1 0.5 MAX 0.31 100 150 -- -- -- -- -- -- 3.45 -- 1000 300 400 50 1 0.6 1 4 2 -- -- FAST-MODE I2C-bus MIN -- 0 50 1.3 0.6 1.3 0.6 0.6 0.6 02 100 20 + 0.1Cb -- -- -- -- -- -- -- 1 0.5
3
UNIT ns kHz kHz s s s s s s s ns ns s s ns s s s s s ns s
MAX 0.31 400 150 -- -- -- -- -- -- 0.9 -- 300 300 400 50 1 0.6 1 4 2 -- --
20 + 0.1Cb3
INT0 and INT1 outputs
NOTES: 1. Pass gate propagation delay is calculated from the 20 typical RON and the 15 pF load capacitance. 2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 3. Cb = total capacitance of one bus line in pF. 4. Measurements taken with 1 k pull-up resistor and 50 pF load. 5. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions. 6. Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.
2004 Oct 01
22
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
Figure 22. Definition of timing on the I2C-bus
handbook, full pagewidth
PROTOCOL
START CONDITION (S)
BIT7 MSB (A7)
BIT6 (A6)
BIT8 (R/W)
ACKNOWLEDGE (A)
STOP CONDITION (S)
t
SU;STA
t
LOW
t HIGH
1 / f SCL
SCL
t
BUF
tr
t
f
SDA
t HD;STA
t
SU;DAT
t
HD;DAT
t
VD;DAT
t
VD;ACK
t
SU;STO
SW02278
Figure 23.
I2C-bus
timing diagram; rise and fall times refer to VIL and VIH
ACK OR READ CYCLE
START SCL
SDA
30% tRESET RESET 50% tREC tW tRESET LEDx 50% 50% 50%
LED OFF
SW02336
Figure 24. Definition of RESET timing 2004 Oct 01 23
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
VDD RL = 500 VI PULSE GENERATOR RT D.U.T. CL VO
6.0 V Open
= 50 pF
DEFINITIONS
RL = Load resistor. CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to the output impedance ZO of the pulse generators.
SW02279
Figure 25. Test circuitry for switching times
2004 Oct 01
24
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
2004 Oct 01
25
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
2004 Oct 01
26
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
2004 Oct 01
27
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
REVISION HISTORY
Rev _2 Date 20041001 Description Product data (9397 750 13629); supersedes data of 02 December 2003 (9397 750 12453). Modifications:
* Table 7 and its description added to page 10. * "Power-On Reset" section on page 13:
- first sentence: change from "... in a reset state until VDD has reached VPOR." to " ... in a reset condition until VDD has reached VPOR." - Add last sentence in section.
* Add Note 1 to DC Characteristics tables on pages 20 and 21, and reference to it at parameter VPOR. * AC characterists table on page 22:
- Add Note 4 and references to it at parameters tVD;DATL and tVD;DATH.
* Add (new) Figure 24, `Definition of RESET timing'.
_1 20031202
- Add Notes 5 and 6 and references to them at parameter tREC:STA
Product data (9397 750 12453); ECN 853-2436 01-A14594 dated 11 November 2003.
2004 Oct 01
28
Philips Semiconductors
Product data sheet
2-to-1 I2C demultiplexer with interrupt logic and reset
PCA9541
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data sheet
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data sheet
Qualification
III
Product data sheet
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 10-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document number:
9397 750 13629
Philips Semiconductors
2004 Oct 01 29

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